Primitive logic gates are part of the Verilog language. Two properties can be specified, drive_strength and delay.
Drive_strength specifies the strength at the gate outputs. The strongest output is a direct connection to a source, next comes a connection through a conducting transistor, then a resistive pull-up/down. The drive strength is usually not specified, in which case the strengths defaults to strong1 and strong0. Refer to Cadence Verilog-XL Reference Man-
ual for more details on strengths.
Delays: If no delay is specified, then the gate has no propagation delay; if two delays are specified, the first represent the rise delay, the second the fall delay; if only one delay is specified, then rise and fall are equal. Delays are ignored in synthesis. This method of specifying delay is a special case of “Parameterized Modules” . The parame-
ters for the primitive gates have been predefined as delays.
Basic Gates
These implement the basic logic gates. They have one output and one or more inputs. In the gate instantiation syntax
shown below, GATE stands for one of the keywords and, nand, or, nor, xor, xnor.
Syntax
GATE (drive_strength) # (delays)
instance_name1(output, input_1,
input_2,…, input_N),
instance_name2(outp,in1, in2,…, inN);
Delays is
#(rise, fall) or
# rise_and_fall or
#(rise_and_fall)
Example 1
buf, not Gates
These implement buffers and inverters, respectively. They have one input and one or more outputs. In the gate instantiation syntax shown below, GATE stands for either the keyword buf or not
Syntax
GATE (drive_strength)#(delays)
instance_name1(output_1, output_2,…, output_n, input),
instance_name2(out1, out2, …, outN, in);
Example 2
Three-State Gates; bufif1, bufif0, notif1, notif0
These implement 3-state buffers and inverters. They propagate z (3-state or high-impedance) if their control signal is deasserted. These can have three delay specifications: a rise time, a fall time, and a time to go into 3-state.
Circuit Diagram Example 3
