Literals
Literals are constant-valued operands that can be used in Verilog expressions. The two common Verilog literals are:
(a) String: A string literal is a one-dimensional array of characters enclosed in double quotes (“ “).
(b) Numeric: constant numbers specified in binary, octal, decimal or hexadecimal.
| Number Syntaxn’Fddd…, wheren – integer representing number of bitsF – one of four possible base formats: b (binary), o (octal), d (decimal). h (hexadecimal). Default is d.dddd – legal digits for the base format |  |
Wires, Regs, and Parameters
Wires, regs and parameters can also be used as operands in Verilog expressions.
Bit-Selects “x[3]” and Part-Selects “x[5:3]”
Bit-selects and part-selects are a selection of a single bit and a group of bits, respectively, from a wire, reg or parameter vector using square brackets “[ ]”. Bit-selects and part-selects can be used as operands in expressions in much the same way that their parent data objects are used.
| Syntax variable_name[index] variable_name[msb:lsb] |  |
Function Calls
The return value of a function can be used directly in an expression without first assigning it to a register or wire variable. Simply place the function call as one of the operands. Make sure you know the bit width of the return value of the function call.
| Syntaxfunction_name (argument_list) |  |
