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| Type Casting In System Verilog :Many Times we require assigning one type of variable to other type variable. Verilog was loosely typed language. The variables could be assigned to other type without any implicit casting. But with system verilog we need to manually cast the variable from one type to the other type otherwise compiler will issue an error. In System verilog there are basically two types of casting 1. Static Casting 2. Dynamic Casting 1. Static Casting A data type can be changed by using a cast ( ‘ ) operation. In a static cast, the expression to be cast shall be enclosed in parentheses that are prefixed with the casting type and an apostrophe. If the expression is assignment compatible with the casting type, then the cast shall return the value that a variable of the casting type would hold after being assigned the expression. Example:- int’(2.0 * 3.0) shortint'{{8’hFA,8’hCE}} 2. Dynamic Casting : SystemVerilog provides the $cast system task to assign values to variables that might not ordinarily be valid because of differing data type. $cast can be called as either a task or a function. The syntax for $cast is as follows: function int $cast( singular dest_var, singular source_exp ); task $cast( singular dest_var, singular source_exp ); The dest_var is the variable to which the assignment is made. The source_exp is the expression that is to be assigned to the destination variable. Use of $cast as either a task or a function determines how invalid assignments are handled. When called as a task, $cast attempts to assign the source expression to the destination variable. If the assignment is invalid, a run-time error occurs, and the destination variable is left unchanged. typedef enum { red, green, blue, yellow, white, black } Colors; Colors col; $cast( col, 2 + 3 ); The following example shows how to use the $cast to check whether an assignment will succeed: if ( ! $cast( col, 2 + 8 ) ) // 10: invalid cast $display( “Error in cast” ); |
