Class Inheritance In System Verilog : #
A class declaration can extend an existing class. Inheritance Subclass inherits all members of parent.
Can over-ride parent’s members Parent members are accessed as if they were members of the subclass
01.class parent;
02.logic [3:0] avec;
03.logic abit;
04.
05.function void print();
06.$display("%d %d", avec, abit);
07.endfunction
08.
09.endclass
10.
11.class child extends parent;
12.int avec;
13.byte abyte;
14.
15.function void print();
16.$display("%0d %b %h", avec, abit, abyte);
17.endfunction
18.
19.endclass
20.
21.program test;
22.
23.child one = new();
24.
25.initial begin
26.one.avec = 0;
27.one.abit = 1'b1;
28.one.abyte = 8'hff;
29.one.print(); // 0 1 ff
30.end
31.
32.endprogram
Parent constructor is implicitly called as first line of subclass constructor. Parent constructor must be explicitly called to pass arguments. Must be the first line of subclass constructor Prefix super allows a subclass to access parent members . Otherwise hidden by subclass members
01.class parent;
02.logic p1;
03.
04.function new(input logic a1);
05.p1 = a1;
06.endfunction
07.
08.endclass
09.
10.class child extends parent;
11.logic c1;
12.
13.function new(input logic a1, a2);
14.super.new(a1);
15.c1 = a2;
16.endfunction
17.
18.function void print();
19.$display("%b %b", p1, c1);
20.endfunction
21.endclass
22.
23.child one = new(1'b0, 1'b0);
24.
25.initial begin
26.one.b1 = 1'b1;
27.one.print(); // 1 0
28....
