System verilog allows prameterized classes. In the system verilog you can parameterize the types also. Its basically like templates in C++. Like in classes can be parameterized for size, width, and more With Verilog parameter notation
Class type can also be a parameter
– Qualified with keyword type
– Define operations which can be used with different types
Each different type parameter creates a different class declaration.
– Separate static members for each different type
Parameterized classes can be extended (inherited).
01.typedef logic[7:0] vec84;
02.
03.class stack #(type st = int, depth = 5);
04.local st data[depth-1:0];
05.local int pointer;
06.
07.function int push(input st indat);
08....
09.endfunction
10.function int pop(output st outdat);
11....
12.endfunction
13.endclass
14.
15.// int stack of depth 5 (default)
16.stack intstack = new();
17.
18.// 8-bit vector stack, depth 8
19.stack #(.st(vec8), .depth(8)) bytestack;
