Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluating
the progress of a verification project in order to reduce the number of simulation cycles spent in verifying a design.
There are two type of the coverage metrics code coverage and functional Code coverage and function coverage tells the verification engineer if the test plan goals have been met or not.
The SystemVerilog functional coverage constructs enable the follow :
- Coverage of variables and expressions, as well as cross cov
- Automatic as well as user-defined coverage bins
- Associate bins with sets of values, transitions, or cross prod
- Filtering conditions at multiple levels
- Events and sequences to automatically trigger coverage sam
- Procedural activation and query of coverage
- Optional directives to control and regulate coverage
