Interview Questions
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SystemVerilog Interview Questions
Last Updated: July 20, 20251. What is the difference between a reg, wire and logic in SystemVerilog?reg and wire are two data types that existed from Verilog, while logic is a new data typethat was introduced in SystemVerilog. 1) A wire is a data type that can model physical wires to connect two elements.Wires can only be driven by...
Verilog Interview Questions
Last Updated: July 12, 20251. Write a verilog code to swap contents of two registers with and without a temporary register? With temp reg ; always @ (posedge clock)begin temp=b;b=a;a=temp;end Without temp reg; always @ (posedge clock)begin a <= b;b <= a;end 2. Difference between blocking and non-blocking? The Verilog language has two forms of the procedural assignment statement: blocking and...