System Verilog
System Verilog Introduction
Last Updated: August 1, 2025What is SystemVerilog? SystemVerilog is a Hardware Description and Verification Language (HDVL) that extends the capabilities of Verilog-2001 (IEEE 1364). It combines powerful design modeling constructs with advanced verification features, making it suitable for both RTL design and functional verification of digital systems. Why SystemVerilog? While Verilog was mainly focused on RTL modeling and synthesis,...
Data Types
Last Updated: August 3, 2025Introduction SystemVerilog enhances Verilog by introducing powerful and flexible data types. These allow better modeling of hardware behavior, efficient simulation, and support for object-oriented testbenches. SystemVerilog data types fall into four main categories: 1. Net Types What are Net Types? Net types represent physical connections in hardware (e.g., wires). They model continuous assignments, like in...
Type Casting
Last Updated: August 3, 2025What is Type Casting? Type casting is the process of converting one data type into another. It is especially useful when working with different bit-widths, enum, struct, or class types. SystemVerilog supports two types of casting: Why Type Casting is Important 1. Static Casting Static casting is used to convert values at compile-time between compatible...
Arrays
Last Updated: May 4, 2025Arrays in system verilog : An array is a collection of variables, all of the same type, and accessed using the same name plus one or more indices. reg [7:0] r1 [1:256]; // [7:0] is the vector width, [1:256] is the array size SystemVerilog uses the term packed array to refer to the dimensions declared before...
Associative Arrays
Last Updated: August 10, 2025What is an Associative Array? An Associative Array is a one-dimensional unpacked array in SystemVerilog where elements are indexed using non-consecutive values such as integers, strings, or even objects. Unlike fixed or dynamic arrays, storage is allocated only when an element is used, making associative arrays ideal for sparse data structures. Syntax: Example: Differences from...
Dynamic Arrays
Last Updated: August 4, 2025What is a Dynamic Array? A Dynamic Array is a one-dimensional unpacked array whose size can be set and changed during simulation runtime using the new[] operator. Unlike fixed arrays, dynamic arrays are ideal when the number of elements is not known in advance, such as in packet-based verification scenarios where the size can vary...
Queue
Last Updated: August 4, 2025What is a Queue? A queue in SystemVerilog is a variable-size, ordered collection of homogeneous elements (i.e., all of the same type). It is a single-dimensional unpacked array that can grow or shrink dynamically during simulation. Unlike fixed-size arrays, queues do not require a predefined upper limit, making them highly useful for scenarios where data...
Operators
Last Updated: August 5, 2025Operators in SystemVerilog Operators are essential tools in any programming or hardware description language. In SystemVerilog, operators are used for arithmetic, logical, bitwise, relational, and conditional operations—just like in software languages such as C/C++, but tailored to hardware modeling. Arithmetic Operators Used to perform basic mathematical operations. Operator Name Description Example + Addition Adds two...
Procedural statements and Control flow
Last Updated: May 4, 2025A procedural statement can be added in system verilog using : SystemVerilog has the following types of control flow within a process:— Selection, loops, and jumps— Task and function calls— Sequential and parallel blocks— Timing control Blocking and Non Blocking Statement : Following type of statement is allowed in both verilog and system verilog. view...
Classes
Last Updated: August 2, 2025What is a Class in SystemVerilog? A class in SystemVerilog is a user-defined data type that combines properties (variables) and methods (functions/tasks). Classes enable object-oriented programming features in SystemVerilog, such as encapsulation, inheritance, and polymorphism—commonly used in testbench development. Why Use Classes? In traditional Verilog, everything is procedural and structural. But when you’re building testbenches,...
Inheritance
Last Updated: August 2, 2025What is Inheritance? Inheritance is a fundamental concept in Object-Oriented Programming (OOP), and SystemVerilog fully supports it through class-based modeling. In simple terms, inheritance allows a class (called the child class) to automatically acquire the properties and behaviors (variables and methods) of another class (called the parent class or base class). This promotes: Syntax: Example:...
Encapsulation
Last Updated: August 2, 2025What is Encapsulation? Encapsulation is an object-oriented programming concept where internal class details (properties and methods) are hidden from outside access. It promotes data protection, modularity, and controlled access to sensitive parts of a class. Access Control in SystemVerilog Classes In SystemVerilog, class properties are public by default — meaning they can be accessed directly...
This and Super operator
Last Updated: August 2, 2025In SystemVerilog, this and super are special object handles used inside class-based code. They help when: What is this? The this keyword is a handle that refers to the current object of the class. Purpose of this Example: Disambiguating variable names Without this keyword, addr = addr; assigns the argument to itself — which is...
In-Line Constraints
Last Updated: May 4, 2025One of the main feature of the systemverilog classes are randomization. You can randomize the system verilog classes with the randomize method using obj.randomize(); It will randomize all the properties which are declared as rand and randc and can take any valid value for the varialbe. like for variable rand bit [3:0] a; A can...
Class Constraints
Last Updated: May 4, 2025Constraints can be declared as class properties. Constraints can enforce dependencies for randomization. Dynamic array is now rand. Both size and contents are randomized, but… …size is randomized first post_randomize and data_rand methods are no longer required. 01.class randframe; 02.local logic [3:0] addr; 03.rand local logic [3:0] len; 04.rand logic [7:0] data_arr []; 05. 06.function new(input logic[3:0] pa); 07.addr = pa; 08.endfunction 09. 10.constraint framelength...
Virtual Classes
Last Updated: May 4, 2025A virtual class is a temple or place holder for the child classes. A virtual class is also called as the abstract class. A virtual class is declared with a virtual keyword like : virtual class base; endclass; A virtual class instance or object can not be constucted but you can define the hadle to...
Parameterized Classes
Last Updated: May 4, 2025System verilog allows prameterized classes. In the system verilog you can parameterize the types also. Its basically like templates in C++. Like in classes can be parameterized for size, width, and more With Verilog parameter notation Class type can also be a parameter – Qualified with keyword type – Define operations which can...
Singleton Classes
Last Updated: May 4, 2025Sometimes it is required to have only one object of some classes like configuration classes. For this purpose we create singleton classes. Only one object is created for a singleton class and whenever we try to create a new object, same object is returned. System verilog does not provide construct to create a singleton class....
Functional Coverage Introduction
Last Updated: May 4, 2025Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluatingthe progress of a verification project in order to reduce the number of simulation cycles spent in verifying a design. There are two type of the coverage metrics code coverage and functional Code coverage and...
Covergroup
Last Updated: May 4, 2025Covergroup is like a user defined type that encapsulates and specifies the coverage. It can be defined in a package, module, program, interface or class Once defined multiple instances can be created using new Parameters to new() enable customization of different instances. A covergroup sepcification can include the following components – Ref argument enables different...
Tools
Last Updated: May 4, 2025Simulators IDE : Free Simulators : Only Verilog 1995 VCD Viewer nWave: One of the best VCD viewer, with support for large VCD dumps. Undertow: Undertow waveform viewer. GTKWave: Freeware VCD viewer, Seems far better then other free VCD viewers. Dinotrace: Freeware VCD viewer from veritools Code Coverage Linting Leda: Leda is a code purification...
Books
Last Updated: May 4, 2025Few Good books on system verilog I know are :1. System verilog LRM2. System verilog for verification : Chris Spear3. System verilog for design