Verilog Tutorial
Verilog Introduction
Last Updated: May 4, 2025Introduction Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDL’s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to...
Lexical Tokens
Last Updated: May 4, 2025Verilog source text files consists of the following lexical tokens:White SpaceWhite spaces separate words and can contain spaces, tabs, new-lines and form feeds. Thus a statement can extend over multiple lines without special continuation characters.CommentsComments can be specified in two ways (exactly the same way as in C/C++): – Begin the comment with double slashes...
Gate-Level Modelling
Last Updated: May 4, 2025Primitive logic gates are part of the Verilog language. Two properties can be specified, drive_strength and delay. Drive_strength specifies the strength at the gate outputs. The strongest output is a direct connection to a source, next comes a connection through a conducting transistor, then a resistive pull-up/down. The drive strength is usually not specified, in...
Data Types
Last Updated: May 4, 2025Value Set Verilog consists of only four basic values. Almost all Verilog data types store all these values:0 (logic zero, or false condition)1 (logic one, or true condition)x (unknown logic value) x and z have limited use for synthesis.z (high impedance state) WireA wire represents a physical wire in a circuit and is used to...
Operators
Last Updated: May 4, 2025Arithmetic OperatorsThese perform arithmetic operations. The + and – can be used as either unary (-z) or binary (x-y) operators. Operators / (division) % (modulus) Verilog Arithmatic Operator Example Relational OperatorsRelational operators compare two operands and return a single bit 1or 0. These operators synthesize into comparators. Wire and reg variables are positive Thus (-3’b001)...
Operands
Last Updated: May 4, 2025Literals Literals are constant-valued operands that can be used in Verilog expressions. The two common Verilog literals are:(a) String: A string literal is a one-dimensional array of characters enclosed in double quotes (“ “).(b) Numeric: constant numbers specified in binary, octal, decimal or hexadecimal. Number Syntaxn’Fddd…, wheren – integer representing number of bitsF – one...
Modules
Last Updated: May 4, 2025Module DeclarationA module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specifies the i/o type (input, output or inout, see Sect. 4.4. ) and width of each port. The default port width is 1 bit.Then the port variables...
Behavioral Modeling
Last Updated: May 4, 2025Verilog has four levels of modelling:1) The switch level which includes MOS transistors modelled as switches. This is not discussed here.2) The gate level. See “Gate-Level Modelling” on p. 33) The Data-Flow level. See Example 7 .4 on page 114) The Behavioral or procedural level described below.Verilog procedural statements are used to model a design...
Timing Controls
Last Updated: May 4, 2025Delay Control Not synthesizable This specifies the delay time units before a statement is executed during simulation. A delay time of zero can also be specified to force the statement to the end of the list of statements to be evaluated at the current simulation time. Syntax #delay statement; Event Control, @This causes a statement...
Procedures: Always and Initial Blocks
Last Updated: May 4, 2025Always Block The always block is the primary construct in RTL modeling. Like the continuous assignment, it is a concurrent statement that is continuously executed during simulation. This also means that all always blocks in a module execute simultaneously. This is very unlike conventional programming languages, in which all statements execute sequentially. The always block...
Functions
Last Updated: May 4, 2025Functions are declared within a module, and can be called from continuous assignments, always blocks or other functions. In a continuous assignment, they are evaluated when any of its declared inputs change. In a procedure, they are evaluated when invoked.Functions describe combinational logic, and by do not generate latches. Thus an if without an else...
Tasks
Last Updated: May 4, 2025Tasks Not SynthesizableA task is similar to a function, but unlike a function it has both input and output ports. Therefore tasks do not return values. Tasks are similar to procedures in most programming languages. The syntax and statements allowed in tasks are those specified for functions (Sections 11). Syntax task task_name; input [msb:lsb] input_port_list; output [msb:lsb] output_port_list; reg [msb:lsb] reg_variable_list; parameter [msb:lsb] parameter_list; integer [msb:lsb] integer_list; ...
Component Inference
Last Updated: May 4, 2025LatchesA latch is inferred (put into the synthesized circuit) if a variable is not assigned to in the else branch of an if … else if … else statement. A latch is also inferred in a case statement if a variable is assigned to in only some of the possible case choice branches. Assigning a...
Finite State Machines.
Last Updated: May 4, 2025Finite State Machines. For synthesisWhen modeling finite state machines, it is recommended to separate the sequential current-state logic from the com- binational next-state and output logic.State Diagram for lack of space the outputs are notshown on the state diagram, but are: in state0: Zot = 000, in state1: Zot = 101, in state2: Zot = 111, in...
Compiler Directives
Last Updated: May 4, 2025Compiler directives are special commands, beginning with ‘, that affect the operation of the Verilog simulator. The Synopsys Verilog HDL Compiler/Design Compiler and many other synthesis tools parse and ignore compiler directives, and hence can be included even in synthesizable models. Refer to Cadence Verilog-XL Reference Manual for a complete listing of these directives. A...
System Tasks and Functions
Last Updated: May 4, 2025These are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($). The Synopsys Verilog HDL Compiler/Design Compiler and many other synthesis tools parse and ignore system functions, and hence can be included even in synthesizable models. Refer to Cadence Verilog-XL Reference Manual for...
Test Benches
Last Updated: May 4, 2025A test bench supplies the signals and dumps the outputs to simulate a Verilog design (module(s)). It invokes the design under test, generates the simulation input vectors, and implements the system tasks to view/format the results of the simulation. It is never synthesized so it can use all Verilog commands. To view the waveforms when using...