Classes

What is a Class in SystemVerilog? #

A class in SystemVerilog is a user-defined data type that combines properties (variables) and methods (functions/tasks). Classes enable object-oriented programming features in SystemVerilog, such as encapsulation, inheritance, and polymorphism—commonly used in testbench development.

Why Use Classes? #

In traditional Verilog, everything is procedural and structural. But when you’re building testbenches, you often need:

• Randomization
• Reusability
• Clean code organization
• Hierarchical modeling

Classes help with all of that. They’re especially important in UVM (Universal Verification Methodology).

How to Define a Class #

class ClassName;
  // Data Members
  // Functions or Tasks
endclass

Example:

class Packet;
  bit [7:0] addr;
  bit [7:0] data;

  function void display();
    $display("Addr = %0h, Data = %0h", addr, data);
  endfunction
endclass

Creating (Allocating) Objects #

In SystemVerilog, classes are dynamic objects.
You must allocate memory using the new keyword.

Example:

Packet p1;        // Declare handle
p1 = new();       // Allocate memory

p1.addr = 8'hA0;
p1.data = 8'h55;
p1.display();

Output:  Addr = A0, Data = 55

Important Features of Classes #