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One of the main feature of the systemverilog classes are randomization. You can randomize the system verilog classes with the randomize method using
obj.randomize();
It will randomize all the properties which are declared as rand and randc and can take any valid value for the varialbe. like for variable
rand bit [3:0] a;
A can take any value between 0 – 15. Constraints can be applied to or used to contol the value generated with randomization. In system verilog constraints can be applied in two ways :
- In line constraints
- Class constraints
Inline constraints can be attached to randomize using with.
– Simple relational constraint
– Change weighting of values with dist
But they are difficult to maintain and a better option is to use subclasses and inheritance.
01.class randframe;
02.local logic [3:0] addr;
03.rand local logic [3:0] len;
04.logic [7:0] data_arr [];
05.
06.function new(input logic [3:0] pa);
07.addr = pa;
08.endfunction
09.
10.function void post_randomize();
11.data_rand();
12.endfunction
13.
14....
15.
16.endclass
17.
18.randframe one = new(.pa(5));
19.
20.initial begin
21.assert(one.randomize() with {len>0; len<=7;});
22....
23.assert(one.randomize() with {len dist {[1:7]:=2, [8:15]:=1};});
24....
