Verilog source text files consists of the following lexical tokens:
White Space
White spaces separate words and can contain spaces, tabs, new-lines and form feeds. Thus a statement can extend over multiple lines without special continuation characters.
Comments
Comments can be specified in two ways (exactly the same way as in C/C++):
– Begin the comment with double slashes (//). All text between these characters and the end of the line will beignored by the Verilog compiler.
– Enclose comments between the characters /* and */. Using this method allows you to continue comments on more than one line. This is good for “commenting out” many lines code, or for very brief in-line comments.
| Example: a = c + d; // this is a simple comment /* however, this comment continues on more than one line */ assign y = temp_reg; assign x=ABC /* plus its compliment*/ + ABC_ |
Numbers
Number storage is defined as a number of bits, but values can be specified in binary, octal, decimal or hexadecimal
Examples are 3’b001, a 3-bit number, 5’d30, (=5’b11110), and 16‘h5ED4, (=16’d24276)
Identifiers
Identifiers are user-defined words for variables, function names, module names, block names and instance names. Identifiers begin with a letter or underscore (Not with a number or $) and can include any number of letters, digits and underscores. Identifiers in Verilog are case-sensitive.
Syntax
allowed symbols
ABCDE . . . abcdef. . . 1234567890 _$
not allowed: anything else especially
– &#@
Operators
Operators are one, two and sometimes three characters used to perform operations on variables.
Examples include >, +, ~, &, !=.
Verilog Keywords
These are words that have special meaning in Verilog. Some examples are assign, case, while, wire, reg, and, or, nand, and module. They should not be used as identifiers. Refer to Cadence Verilog-XL Reference Manual for a complete listing of Verilog keywords. A number of them will be introduced in this manual. Verilog keywords also
includes Compiler Directives and System Tasks and Functions .
