Data Types

Introduction #

SystemVerilog enhances Verilog by introducing powerful and flexible data types. These allow better modeling of hardware behavior, efficient simulation, and support for object-oriented testbenches.

SystemVerilog data types fall into four main categories:

1. Net Types
2. Variable Types
3. User-Defined Types
4. Special Types (Queue, Enum, Struct, etc.)

1. Net Types #

What are Net Types?

Net types represent physical connections in hardware (e.g., wires). They model continuous assignments, like in combinational circuits.

Example:

wire a, b, c;
assign c = a & b; // Continuous assignment

2. Variable Types #

What are Variable Types?

These are procedural storage types, used in always, initial, function, and task blocks. They hold values until explicitly changed.

SystemVerilog offers:

4-state types: can take values 0, 1, x, z

2-state types: only 0 or 1 (faster simulation)

4-State Variable Types

2-State Variable Types

Example:

logic [3:0] a;       // 4-bit logic type
bit       enable;    // 1-bit, only 0 or 1
int       counter;   // 32-bit signed integer

3. User-Defined Types #

SystemVerilog allows creating your own types for better abstraction and reusability.

typedef #

Used to define a new name for an existing type.

typedef logic [7:0] byte_t;
byte_t data;

enum (Enumeration) #

Defines a set of named values (states, modes, etc.)

typedef enum {IDLE, READ, WRITE} state_t;
state_t current_state;

struct #

Used to group multiple related variables.

typedef struct {
  logic [7:0] addr;
  logic [7:0] data;
} packet_t;

packet_t pkt;

union #

Overlays multiple members in the same memory location.

typedef union {
  logic [15:0] half_word;
  logic [7:0]  bytes[2];
} data_u;

4. Special Types #

queue #

A dynamic, indexable array that can grow or shrink.

int queue1[$];        // Unbounded queue
queue1.push_back(10); // Add at end
queue1.pop_front();   // Remove from front

string #

Used to store text data.

string name = "SystemVerilog";
$display("Hello, %s", name);