Operators

Operators in SystemVerilog #

Operators are essential tools in any programming or hardware description language. In SystemVerilog, operators are used for arithmetic, logical, bitwise, relational, and conditional operations—just like in software languages such as C/C++, but tailored to hardware modeling.

Arithmetic Operators #

Used to perform basic mathematical operations.

Example:

module arithmetic_example;
  int a = 15;
  int b = 4;

  initial begin
    $display("Addition:       a + b = %0d", a + b); 
    $display("Subtraction:    a - b = %0d", a - b); 
    $display("Multiplication: a * b = %0d", a * b); 
    $display("Division:       a / b = %0d", a / b); 
    $display("Modulus:        a % b = %0d", a % b); 
  end
endmodule

Output:

Addition:       a + b = 19
Subtraction:    a - b = 11
Multiplication: a * b = 60
Division:       a / b = 3
Modulus:        a % b = 3

Relational Operators #

Relational operators are used to compare values. They return 1 (true) or 0 (false) and are often used in conditional expressions like if, while, assert, etc.

Example:

module relational_example;
  int a = 10;
  int b = 20;

  initial begin
    $display("a <  b : %0d", a <  b);
    $display("a <= b : %0d", a <= b);  
    $display("a >  b : %0d", a >  b);  
    $display("a >= b : %0d", a >= b);  
  end
endmodule

Output:

a <  b : 1
a <= b : 1
a >  b : 0
a >= b : 0

Equality Operators #

Compare two values for equality or inequality.

Example:

module equality_operator;

  logic [3:0] a, b, c;

  initial begin
    // Initialize values
    a = 4'b1x0z;   // Contains x and z
    b = 4'b1x0z;   // Same as a
    c = 4'b1001;   // Different from a,b

    $display("a = %b, b = %b, c = %b", a, b, c);

    // == and != ignore x/z values (result may be unknown 'x')
    $display("a == b  : %0d", a == b);   
    $display("a != c  : %0d", a != c);  

    // === and !== compare bits exactly including x/z
    $display("a === b : %0d", a === b);  
    $display("a !== c : %0d", a !== c);  
  end

endmodule

Output:

a = 1x0z, b = 1x0z, c = 1001
a == b  : x
a != c  : x
a === b : 1
a !== c : 1

Shift Operators #

Used for shifting bits left or right.

Example:

module shift_operator;

  logic [7:0] a = 8'b00110110;    // unsigned
  logic signed [7:0] b = -8'sd28; // signed: 8'b11100100

  initial begin
    $display("Original a  = %b", a);
    $display("a << 2      = %b", a << 2);   // Logical left shift
    $display("a >> 2      = %b", a >> 2);   // Logical right shift

    $display("Original b  = %b (%0d)", b, b);
    $display("b <<< 2   = %b (%0d)", b <<< 2, b <<< 2); // Arithmetic left shift
    $display("b >>> 2   = %b (%0d)", b >>> 2, b >>> 2); // Arithmetic right shift
  end

endmodule

Output:

Original a     = 00110110
a << 2         = 11011000
a >> 2         = 00001101
Original b     = 11100100 (-28)
b <<< 2        = 10010000 (-112)
b >>> 2        = 11111001 (-7)

Concatenation Operator {} #

Concatenation joins multiple signals, constants, or expressions into a single vector.

Syntax:

{expr1, expr2, expr3, ...}

Example:

module concat_example;
  logic [3:0] a = 4'b1010;
  logic [3:0] b = 4'b0101;
  logic [7:0] result;

  initial begin
    result = {a, b};  // Concatenates a and b 
    $display("Concatenation: %b", result);
  end
endmodule

Output:

Concatenation: 10100101

Replication Operator {n{expr}} #

Replication repeats a value or expression n times.

Syntax:

{N{expression}}

Example:

module replication_example;
  logic [1:0] x = 2'b11;
  logic [5:0] result;

  initial begin
    result = {3{x}};  // Replicates x 3 times => 6'b111111
    $display("Replication: %b", result);
  end
endmodule

Output:

Replication: 111111