1. What is the difference between a reg, wire and logic in SystemVerilog?
reg and wire are two data types that existed from Verilog, while logic is a new data type
that was introduced in SystemVerilog.
1) A wire is a data type that can model physical wires to connect two elements.
Wires can only be driven by continuous assignment statement and cannot hold onto
value if not driven. Wires can hence only be used to model combinational logic.
2) A reg is a data type that can model a storage element or a state. They need to be
driven by an always block and cannot be driven by continuous assignment
statement. A reg can be used to model both sequential and combinational logic
3) A logic is a new data type in SystemVerilog that can be used to model both
wires and state information (reg). It also is a 4 state variable and hence can hold 0,
1, x and z values. If a wire is declared as a logic (wire logic), then it can be used to
model multiple drivers and the last assignment will take the value.
2. What is the difference between a bit and logic data type?
bit is a 2-state data type that can take only values 0 and 1, while logic is a 4-state data type
which can take values 0, 1, x, and z.
2-state variables will help in a small simulation speed up but should not be used if it is
used to drive or sample signals from RTL design in which uninitialized and unknown
values will be missed.
3. What is the difference between logic[7:0] and byte variable in
SystemVerilog?
byte is a signed variable which means it can only be used to count values till 127. A
logic[7:0] variable can be used for an unsigned 8 bit variable that can count up to 255.
4. Which of the array types: dynamic array or associative array, are good
to model really large arrays, say: a huge memory array of 32KB?
Associative arrays are better to model large arrays as memory is allocated only when an
entry is written into the array. Dynamic arrays on the other hand need memory to be
allocated and initialized before using.
For example: If you want a memory array of 32KB to be modelled using dynamic array,
you would first need to allocate 32K entries and use the array for read/write. Associative
arrays doesn’t need allocation and initialization of memory upfront and can be allocated
and initialized just when an entry of the 32K array needs to be referenced..
However, associative arrays are also slowest as they internally implement search for
elements in the array using a hash.
5. Suppose a dynamic array of integers ( myvalues ) is initialized to values
as shown below. Write a code to find all elements greater than 3 in the
array using array locator method “ find ”?
int myvalues [] = ‘{9,1,8,3,2,4,6},
int match_q[$];
match_q = myvalues.find with (item > 3);
6. What is the difference between a struct and union in SystemVerilog?
A structure represents a collection of data types that can be referenced as a whole, or the
individual data types that make up the structure can be referenced by name. For example:
in the example below, we have a struct defined called instruction_s that groups a 24 bit
address field and an 8 bit opcode field.
typedef struct {
bit [7:0] opcode;
bit [23:0] addr;
} instruction_s
instruction_s current_instruction;
current_instruction.addr=’h100;
The instruction_s struct can be referenced together or individual members can be
accessed. The total memory allocated would be the sum of memory needed for all the data
types. Hence in above example, the currect_instruction struct would take a total memory
of 32 bits (24 bit address and 8 bit opcode)
A union is a data type which can be accessed using one and only one of the named
member data type. Unlike struct you cannot access all member data types together. The
memory allocated for the union would be the maximum of the memory needed for the
member data types. Unions are normally useful if you want to model a hardware resource
like register that can store values of different types. For example: if a register can store an integer and a real values, you can define a union as follows:
typedef union {
int data;
real f_data;
} state_u;
state_u reg_state;
reg_state.f_data = ‘hFFFF_FFFF_FFFF_FFFF;
$display(“ int_data =%h“, reg_state.data);
In this example, the union state_u can either hold a 32 bit integer data or it can hold 64 bit
real data. Hence, the memory allocated for the union reg_state will be 64 bits (bigger of
the two data types). Since, there is shared memory for all member data types, in above
example, if we assign a 64 bit value to reg_state.f_data, we will be also able to reference
the 32 bit of same using the other data type.
7. What is the difference between a packed array and an unpacked array?
A packed array represents a contiguous set of bits while an unpacked array need not be
represented as a contiguous set of bits. In terms of difference in declarations, following is
how a packed and unpacked array is declared
bit [7:0] data ; // packed array of scalar bit types
real latency [7:0]; // unpacked array of real types
Packed arrays can be made of only the single bit data types (bit, logic, reg), or enumerated
types.
Example: logic[31:0] addr; //packed array of logic type
Unpacked arrays can be made of any data type. Example:
class record_c;
record_c table[7:0]; //unpacked array of record objects
8. Which of the following statement is true?
1) Functions should execute in Zero Simulation Time.
2) Tasks should execute in Zero Simulation Time.
1) True
2) False
Functions always need to be executed in zero simulation time and cannot contain any
construct that can induce a time delay (Example: waiting for clock edge or # delays etc.).
Tasks can have constructs causing timing delays and hence, need not complete execution
in zero time.
9. Given a dynamic array of size 100, how can the array be re-sized to hold
200 elements while the lower 100 elements are preserved as original?
A dynamic array needs memory allocation using new[] to hold elements. Here is an
example with an integer array that grows from an initial size of 100 elements to 200
elements.
integer addr[]; // Declare the dynamic array.
addr = new[100]; // Create a 100-element array.
………
// Double the array size, preserving previous values.
addr = new[200];
10. What is the difference between “forever” and “for” in SystemVerilog ?
The “forever” loop repeatedly executes a statement without any limit. The only way
execution can stop is by using a break statement. A forever loop if used without any
timing controls (like clock or time delay) can result in a zero-delay infinite loop and cause
hang in simulation.
The “for” loop is used for executing a statement for a defined number of times based on
conditions that are defined.
11. What is the difference between $display, $write, $monitor and $strobe in
SystemVerilog?
1) $display : Print the values immediately when executed.
2) $strobe : Print the values at the end of the current timestep.
3) $monitor : Print the values at the end of the current timestep if any values
change. If $monitor is called more than once, the last call will override previous
one.
4) $write : This is same as $display but doesn’t terminate with a newline (\n).
12. What is wrong with following SystemVerilog code?
task wait_packet;
Packet packet;
event packet_received;
@packet_received;
packet = new();
endtask
function void do_print();
wait_packet();
$display(“packet received“)
endfunction
A function cannot have any construct that consumes time. In above example, the
function do_print() is calling a task which consumes time. Hence, this is illegal.
A proper fix is to have the function do_print() be called inside the task to print packet
after it is received.
13. What is the difference between new() and new[] in SystemVerilog?
The function new() is the class constructor function in SystemVerilog. It is defined in a
class to initialize data members of the class.
The new[] operator is used to allocate memory for a dynamic array. The size of the
dynamic array that needs to be created is passed as an argument to the new[] .
14. What is the concept of forward declaration of a class in SystemVerilog?
Sometimes a class might reference another class which is not fully defined in the compile
order. This can cause a compile error. For Example: If two classes Statistics and Packet are defined in following order, then while compiling Statistics class, the definition of packet is not yet seen and compiler will fail.
class Statistics;
Packet p1;
endclass
class Packet;
//full definition here
endclass
To avoid this problem, the Packet Class can be forward declared before the full definition.
This concept is called forward declaration.
typedef Packet; //forward declaration
class Statistics;
Packet p1;
endclass
class Packet;
//full definition here
endclass
15. What is the difference between private, public and protected data
members of a SystemVerilog class?
1) Private data members of a class can only be accessed from within the class.
These data members will not be visible in derived classes.
2) Public members can be accessed from within the class as well as outside the
class also. These are also visible in derived classes.
3) Protected data members are similar to private members in the sense that they
are only accessible within the class. However, unlike private members, these are
also visible in derived classes.
16. Are SystemVerilog class members public or private by default ?
SystemVerilog class members are public by-default, unlike other languages like C++/Java
which have default data members as private.
17. What are interfaces in SystemVerilog?
The interface construct in SystemVerilog is a named bundle of nets of variables which
helps in encapsulating communication between multiple design blocks. An interface can
be instantiated in a design and can be connected using a single name instead of having all
the port names and connections.
In addition to connectivity, functionality can also be abstracted in an interface as it
supports defining functions that can be called by instantiating design for communication.
Interfaces also support procedural ( always/initial blocks) and continuous assignments
which are useful for verification in terms of adding protocol checks and assertions.
Following is a simple example on how an interface can be defined.
interface simple_bus; // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus
18. What is a modport construct in an interface?
modport (short form for module port) is a construct in an interface that let you group
signals and specify directions. Following is an example of how an interface can be further
grouped using modports for connecting to different components.
interface arb_if(input bit clk);
logic [1:0] grant, request;
logic reset;
modport TEST (output request, reset, input grant, clk);
modport DUT (input request, reset, clk, output grant);
modport MONITOR (input request, grant, reset, clk);
endinterface
In this example, you can see that the same signals are given different directions in
different modports. A monitor component needs all signals as input and hence the modport
MONITOR of interface can be used to connect to monitor. A test or a driver will need to
drive some signals and sample other signals and above example shows a modport TEST
that can be used.
19. Are interfaces synthesizable?
Yes, interfaces are synthesizable.
20. What is a unique constraint in SystemVerilog?
A unique constraint is used to randomize a group of variables such that no two members
of the group have the same value. Following shows an example: Here a class has a random
array of bytes ( a ) and one another byte ( b ). The unique constraint in this example shows
how unique values can be generated for all of these.
class Test;
rand byte a[5];
rand byte b;
constraint ab_cons { unique {b, a[0:5]}; }
endclass
21. Given a Packet class with following constraints, how can we generate a
packet object with address value greater than 200?
class Packet;
rand bit[31:0] addr;
constraint c_addr { addr inside [0:100];}
endclass
Since default constraint restricts address to be less than 100, we will need to use inline
constraints and turn off default constraint as below:
Packet p = new();
p.c_addr.constraint_mode(0);
p.randomize with {addr > 200;};
22. What are pre_randomize() and post_randomize() functions?
These are built-in callback functions supported in SystemVerilog language to perform an
action immediately either before every randomize call or immediately after randomize call.
A pre_randomize() is useful for setting or overriding any constraints while
a post_randomize() is useful to override results of a randomization.
23. What are system tasks and functions? Give some example of system
tasks and functions with their purpose.
SystemVerilog language supports a number of built-in system tasks and functions for
different utilities and are generally called with a “$” prefix to the task/function name. In
addition, language also supports addition of user defined system tasks and functions.
Following are some examples of system tasks and functions (categorized based on
functionality). For a complete list, one should refer to LRM.
1) Simulation control tasks – $finish, $stop, $exit
2) Conversion functions – $bitstoreal, $itor, $cast
3) Bit vector system functions – $countones, $onehot, $isunknown
4) Severity tasks – $error, $fatal, $warning
5) Sampled value system functions – $rose, $fell, $changed
6) Assertion control tasks – $asserton, $assertoff
24. What is the difference between “DPI import” and “DPI export”?
A DPI imported function is a function that is implemented in the C language and called
in the SystemVerilog code.
A DPI exported function is a function that is implemented in the SystemVerilog language
and exported to C language such that it can be called from C language.
Both functions and tasks can be either imported or exported.
25. What is the concept of callback?
A “callback” is any function that is called by another function which takes the first
function as an argument. Most of the times, a callback function is called when some
“event” happens.
In a Verification testbench, this feature is useful for several applications:
1) Calling back a function to inject error on transactions sent from a driver
2) When a simulation phase is ready to end, calling a function to drain all pending
transactions in all sequence/driver.
3) Calling a coverage sample function on a specific event.
Most of the times, callback functions are implemented by registering them with a
component/object that calls back on some defined conditions.
An example call back function in UVM is phase_ready_to_end() which is implemented in
the base class and is registered with the UVM_component class. The function gets called
when the current simulation phase is ready to end always. Hence, a user can implement
any functionality that needs to be executed at end of a simulation phase by overriding this
function definition.
26. Is it possible to override a constraint defined in the base class in a
derived class and if so how?
Yes, a constraint defined in the base class can be overridden in a derived class by changing
the definition using the same constraint name. For Example: Refer the constraint
c_a_b_const in following code. In the base class, it is defined to always have a value of a
< b, but in a derived class, it has been overridden to have always a > b .
class Base;
rand int a ;
rand int b;
constraint c_a_b_const {
a < b; } endclass class Derived extends Base; constraint c_a_b_const { a > b;
}
endclass
27. How can we merge two events in SystemVerilog?
An event variable can be assigned to another event variable. When an event variable is
assigned to other, both the events point to same synchronization object and are said to be
merged.
28.What are Mailboxes? What are the uses of a Mailbox?
A mailbox is a communication mechanism that allows messages to be exchanged between
processes. Data can be sent to a mailbox by one process and retrieved by another.
Following is an example of declaring and creating a mailbox:
mailbox mbx;
mbx = new();
To place a message in a mailbox, two methods are supported put() (blocking) and peek()
(nonblocking). To retrieve a message from mailbox, two methods are supported get()
(blocking) and try_get() (nonblocking). To retrieve the number of messages in the
mailbox, we can use num().
29. What does keyword “extends” represent in SystemVerilog?
The “extends” keyword is used in class definition to specify the class from which the class
is derived.
For Example: class child extends parent; // means class child is derived from class parent.
